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1 of 28 rev: 071305 note: some revisions of this device may incorporate deviations from published specifications known as errata. m ultiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds3150 performs all the functions necessary for interfacing at the physical layer to ds3, e3, and sts-1 lines. the receiver performs clock and data recovery, b3zs/hdb3 decodi ng, and loss-of-signal monitoring. the transmitter encodes outgoing data and drives standards-compliant waveforms onto 75 ? coaxial cable. the jitter attenuator can be mapped into the receive path or the transmit path. applications sonet/sdh and pdh multiplexers digital cross-connects access concentrators atm and frame relay equipment routers pbxs dslams csus/dsus ordering information part temp range pin-package ds3150qn -40 c to +85 c 28 plcc ds3150q 0 c to +70 c 28 plcc ds3150tn -40 c to +85 c 48 tqfp ds3150t 0 c to +70 c 48 tqfp functional diagram features integrated transmitter, receiver, and jitter attenuator for ds3, e3, and sts-1 performs receive clock/data recovery and transmit waveshaping jitter attenuator can be placed in the receive path or the transmit path agc/equalizer block handles from 0db to 15db of cable loss interfaces to 75 coaxial cable at lengths up to 380m (ds3), 440m (e3), or 360m (sts-1) interfaces directly to a dsx monitor signal (20db flat loss) using built-in preamp built-in b3zs and hdb3 encoder/decoder bipolar and nrz interfaces local and remote loopbacks on-board 2 15 - 1 and 2 23 - 1 pseudorandom bit sequence (prbs) generator and detector line build-out (lbo) control transmit line-driver monitor checks for a faulty transmitter or a shorted output complete ds3 ais generator (ansi t1.107) unframed all-ones generator (e3 ais) clock inversion for glueless interfacing tri-state line driver for low-power mode and protection switching applications loss-of-signal (los) detector (ansi t1.231 and itu g.775) automatic data squelching during los requires minimal external components drop-in replacement for tdk 78p2241/b and 78p7200l (refer to application note 362 ) pin compatible with tdk 78p7200 3.3v operation (5v tolerant i/o), 110ma (max) industrial temperature range: -40 c to +85 c small packaging: 28-pin plcc and 48-pin tqfp pin configurations appear at end of data sheet. ds3150 3.3v, ds3/e3/sts-1 line interface unit www.maxim-ic.com demo kit available rx+ rx- tx+ tx- rclk line in ds3, e3, sts-1 line ou t ds3, e3, sts-1 ds3150 liu rpos rneg tclk tpos tneg receive clock and data transmit clock and data downloaded from: http:///
ds3150 2 of 28 table of contents 1. detailed description.................................................................................................4 1.1 r eceiver .................................................................................................................................... 7 1.2 t ransmitter .............................................................................................................................10 1.3 d iagnostics ..............................................................................................................................1 5 1.4 j itter a ttenuator ...................................................................................................................16 2. pin descri ptions ........................................................................................................17 3. electrical characteristics ................................................................................21 4. pin configurations ..................................................................................................25 5. package information..............................................................................................26 6. revision hi story ........................................................................................................28 downloaded from: http:///
ds3150 3 of 28 list of figures figure 1-1. block diagram ...................................................................................................... .....4 figure 1-2. external connections.................................................................................................6 figure 1-3. receiver jitter tolerance.......................................................................................... .9 figure 1-4. e3 waveform template ...........................................................................................13 figure 1-5. ds3 ais structure .................................................................................................. .14 figure 1-6. prbs output with normal rclk operation ............................................................15 figure 1-7. prbs output with inverted rclk operation...........................................................15 figure 1-8. jitter attenuation and jitter transfer........................................................................16 figure 3-1. framer interface timing diagram ............................................................................22 list of tables table 1-a. applicable telecommunications standards................................................................5 table 1-b. transformer recommendations .................................................................................6 table 1-c. ds3 waveform template .........................................................................................11 table 1-d. ds3 waveform test parameters and limits ............................................................11 table 1-e. sts-1 waveform template ......................................................................................12 table 1-f. sts-1 waveform test parameters and limits .........................................................12 table 1-g. e3 waveform test parameters and limits...............................................................13 table 2-a. pin descriptions.................................................................................................... ....17 table 2-b. transmit data selection ...........................................................................................20 table 2-c. rmon and tts signal decode ................................................................................20 downloaded from: http:///
ds3150 4 of 28 1. detailed description the ds3150 performs all the functions necessary for in terfacing at the physical layer to ds3, e3, and sts-1 lines. the device has independent receive a nd transmit paths and a bu ilt-in jitter attenuator ( figure 1-1 ). the receiver performs clock and data recovery from a b3zs- or hdb3-coded alternate mark inversion (ami) signal and monitors for loss-of-signal. the receiver optionally performs b3zs/hdb3 decoding and outputs the recovered data in either nrz or bipolar format. the transmitter accepts data in either nrz or bipolar format, optionally performs b3 zs/hdb3 encoding, and drives standards-compliant waveforms onto the outgoing 75 ? coaxial cable. the jitter attenuator can be mapped into the receiver data path, mapped into the transmitter data path, or disabl ed. the ds3150 conforms to the telecommunication standards listed in table 1-a . figure 1-2 shows the external components required for proper operation. figure 1-1. block diagram analog loopback pre amp filter/ equalizer (analog loss of signal detect) clock & data recovery line driver wave- shaping clock invert clock invert rx+ rx- tx+ tx- t ts prbs lbo z cse ice tpos/tnrz tclk tneg tess rneg/rlcv rclk rpos/rnrz l os mclk rmon remote loopback efe v dd v ss power connections test functions tds0 tds1 b3zs/ hdb3 encoder ais/ 1010.../ prbs generation mux mux mux prbs detector b3zs/hdb3 decoder digital loss of signal detector squelch jitter attenuator (can be placed in either the receive path or the transmit path) driver monitor output decode loopback control d m l bks ds3150 downloaded from: http:///
ds3150 5 of 28 table 1-a. applicable telecommunications standards specification specification title ansi t1.102-1993 digital hierarchy?electrical interfaces t1.107-1995 digital hierarchy?formats specification t1.231-1997 digital hierarchy?layer 1 in-servi ce digital transmission performance monitoring t1.404-1994 network-to-customer installation?ds3 metallic interface specification itu-t g.703 physical/electrical characteristics of hierarchical digital interfaces, 1991 g.751 digital multiplex equipment operating at the third-order bit rate of 34,368kbps and the fourth-order bit rate of 139,264kbps and using positive justification, 1993 g.775 loss-of-signal (los) and alarm indica tion signal (ais) defect detection and clearance criteria , november 1994 g.823 the control of jitter and wander within digital networks which are based on the 2048kbps hierarchy , 1993 g.824 the control of jitter and wander within digital networks which are based on the 1544kbps hierarchy , 1993 o.151 error performance measuring equipment operating at the primary rate and above , october 1992 etsi ets 300 686 business telecommunications; 34mbps and 140mbps digital leased lines (d34u, d34s, d140u, and d140s); network interface presentation, 1996 ets 300 687 business telecommunications; 34mbps digital leased lines (d34u and d34s); connection characteristics , 1996 ets en 300 689 access and terminals (at); 34mbps digital leased lines (d34u and d34s); terminal equipment interface, july 2001 tbr 24 business telecommunications; 34mbps digita l unstructured and structured lease lines; attachment requirements fo r terminal equipment interface , 1997 telcordia gr-253-core sonet transport systems: common generic criteria , issue 2, december 1995 gr-499-core transport systems generic requireme nts (tsgr): common requirements, issue 2, december 1998 downloaded from: http:///
ds3150 6 of 28 figure 1-2. external connections table 1-b. transformer recommendations manufacturer part no. temp range pin- package/ schematic ocl primary h min l l h max bandwidth 75 , mhz pulse engineering pe-65968 0c to +70c 6-smt ls-1/c 19 0.06 0.250 to 500 pulse engineering pe-65969 0c to +70c 6-thru-hole lc-1/c 19 0.06 0.250 to 500 halo electronics tg07- 0206ns 0c to +70c 6-smt smd/b 19 0.06 0.250 to 500 halo electronics td07- 0206ne 0c to +70c 6-dip dip/b 19 0.06 0.250 to 500 note: table subject to change. industrial temperature range and dual transformers also available. contact the manuf acturers for deta ils. 1:2ct 1:2ct 0.05f transmit receive tx+ tx- rx+ rx- 0.01f 3.3v power plane ground plane v dd v dd v dd v ss v ss v ss ds3150 0.1f 1f 330 (1%) 0.05f 330 (1%) 0.01f 0.1f 1f 0.01f 0.1f 1f v dd downloaded from: http:///
ds3150 7 of 28 1.1 receiver interfacing to the line. the receiver can be transformer-coupled or capacitor-coupled to the line. typically, the receiver interfaces to the incoming coaxial cable (75 ) through a 1:2 step-up transformer. figure 1-2 shows the arrangement of the transformer an d other recommended interface components. the device expects the incoming signal to be in b3zs- or hdb3-coded ami format. optional preamp. the receiver can be used in monitoring a pplications, which typically have series resistors that result in a resistiv e loss of approximately 20db. when the rmon input pin is high, the receiver compensates for this resistive loss by applying flat gain to the incoming sign al before sending the signal to the equalizer block. adaptive equalizer. the adaptive equalizer applies both frequenc y-dependent gain and flat gain to offset signal losses from the coaxial cable and provides a signal of nominal amplitude and pulse shape to the clock and data recovery block. the equalizer circuitry automatically adapts to coaxial cable losses from 0 to 15db, which translates into 0 to 380 meters (ds3), 0 to 440 meters (e3), or 0 to 360 meters (sts-1) of coaxial cable (at&t 734a or equivalent). the equalizer can perform direct (0 meter) monitoring of the transmitter output signal. clock and data recovery. the clock and data recovery (cdr) block takes the amplified, equalized signal from the equalizer and produces separate cloc k, positive data and negative data signals. the cdr requires a master clock (44.736mhz for ds3, 34.368mhz for e3, 51.840mhz for sts-1). if the signal on mclk is toggling, the device selects the mclk signal as the master clock. if mclk is wired high or left floating, the device uses the signal on the tclk pin as the master clock. if mclk is wired low, the device takes its master clock from an internal oscillator. the selected master clock is also used by the jitter attenuator. loss-of-signal detector. the receiver contains both analog and digital los detectors. the analog los detector resides in the equalizer block. if the incoming signal level is less than a signal level approximately 24db below nominal, analog loss-of-sig nal (alos) is declared. the alos signal cannot be directly examined, but when alos occurs the equa lizer squelches the recovere d data, forcing all zeros out of the clock and data recovery circuitry and subsequently causing dig ital loss-of-signal (dlos), which is indicated on the los pin. alos clears when the incoming signal level is greater than or equal to a signal level approxima tely 18db below nominal. the digital loss-of-signal detector declares dlos when it detects 175 75 consecutive zeros in the recovered data stream. when dlos occurs, the receiver asserts the los pin. dlos is cleared when there are no excessive zero occurrences over a span of 175 75 clock periods. an excessive zero occurrence is defined as three or more consecutive zeros in the ds3 and sts-1 modes and f our or more consecutive zeros in the e3 mode. the los pin is deasserted when the dlos condition is cleared. the requirements of ansi t1.231 and itu-t g.775 for ds3 los defects are met by the dlos detector, which asserts los when it counts 175 75 consecutive zeros coming out of the clock and data recovery block and clears los when it counts 175 75 consecutive pulse intervals without excessive zero occurrences. the requirements of itu-t g.775 for e3 los defects are met by a combination of the alos detector and the dlos detector as follows: downloaded from: http:///
ds3150 8 of 28 for e3 lo s assertion: 1) the alos circuitry detects that the incoming signal is less than or equal to a signal level approximately 24db below nominal and mutes the data coming out of the clock and data recovery block. (24db below nominal is in the ?tolerance range? of g.775, where los may or may not be declared.) 2) the dlos detector counts 175 75 consecutive zeros coming out of the clock and data recovery block and asserts los . (175 75 meets the 10 n 255 pulse interval dur ation requirement of g.775.) for e3 lo s clear: 1) the alos circuitry detects that the incoming signal is greater than or equal to a signal level approximately 18db below nominal a nd enables data to come out of the clock and data recovery block. (18db below nominal is in the ?tolerance range? of g.775 where los may or may not be declared.) 2) the dlos detector counts 175 75 consecutive pulse intervals wit hout excessive zero occurrences and deasserts los . (175 75 meets the 10 n 255 pulse interval duratio n requirement of g.775.) the requirements of ansi t1.231 for sts-1 los def ects are supported by the dlos detector. at sts-1 rate, the time required for the dlos detector to count 175 75 consecutive zeros falls in the range of 2.3 t 100 s required by ansi t1.231 for declaring an los defect. although the time required for the dlos detector to count 175 75 consecutive pulse intervals with no excessive zeros is less than the 125s to 250 s period required by ansi t1.231 for clearing an los defect, a period of this length where los is inactive can easily be timed in software. during los, the rclk output signal is derived from the device?s master clock. the alos detector has a longer time constant than the dlos detector. thus, when the incoming signal is lost, the dlos detector activates first, asserting the los pin, followed by the alos detector . when a signal is restored, the dlos detector does not get a valid signal that it can qualify for no excessive zero occurrences until the alos detector has seen the incoming signal rise above a signal level approximately 18db below nominal. framer interface format a nd the b3zs/hdb3 decoder. the recovered data can be output in either nrz or bipolar format. to select the bipolar format, wire the zcse input pin high. in this format, the b3zs/hdb3 decoder is disabled, and the recove red data is buffered and output on the rpos and rneg output pins. received positive-polarity pulses are indicated by rpos = 1, while negative-polarity pulses are indicated by rneg = 1. in bipolar interface format the receiver simply passes on the data received and does not check it for bipolar violations or excessive zero occurrences. to select the nrz format, wire zcse low. in this format, the b3zs/hdb3 decoder is enabled, and the recovered data is decoded and output as a composite nrz value on the rnrz pin. code violations are flagged on the rlcv pin. in the discussion that follows , a valid pulse that conforms to the ami rule is denoted as b. a pulse that violates the ami rule is known as bipolar violation (bpv ) and is denoted as v. in ds3 and sts-1 modes, b3zs decoding is perfor med. rlcv is asserted during any rclk cycle where the data on rnrz causes ones of the following code violations: a bpv immediately preceded by a valid pulse (b, v) a bpv with the same polarity as the last bpv downloaded from: http:///
ds3150 9 of 28 a third consecutive zero (0, 0, 0) in e3 mode, hdb3 decoding is performed. rlcv is asserted during any rclk cycle where the data on rnrz causes one of the following code violations: a bpv immediately preceded by a valid pulse (b, v) or by a valid pulse and a zero (b, 0, v) a bpv with the same polarity as the last bpv a fourth consecutive zero (0, 0, 0, 0) when rlcv is asserted to flag a bpv, the rnrz pin outputs a 1. the state bit that tracks the polarity of the last bpv is toggled on every bpv, whethe r part of a valid b3zs/hdb3 codeword or not. to support a glueless interface to a variety of neig hboring components, the polarity of rclk can be inverted using the ice input pin. see the ice pin description in table 2-a for details. receiver jitter tolerance. the receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in table 1-a . see the graphs in figure 1-3 . receiver jitter transfer. the jitter transfer performance of the receiver, with and without the jitter attenuator enabled, is shown in figure 1-8 . figure 1-3. receive r jitter tolerance e3 jitter tolerance 0.01 0.1 1 10 100 0.1 1 10 100 1000 frequency (khz) ui p-p g.823 and etsi 300 689 ja in r x ja disabled ds3 jitter tolerance 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 frequency (khz) ui p-p g r-4 99 cat ii g.824 g r-4 99 cat i ja in rx ja disable d sts-1 jitter tolerance 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 frequency (khz) ui p-p gr-253-core ja in rx ja disabled note 1: all jitter tolerance curves are worst case over temperature, voltage, cable length (0 to 900 feet), and rmon pin setting. note 2: the low-frequency plateau seen in most of the jitter tolerance curves is not the actual performance of the ds3150 but rather the limit of the measuring equipment (64 ui p-p ). actual jitter tolerance in these low-frequency ranges is greater than or equal to 64 ui p-p . note 3: receiver jitter tolerance is not tested during production test. downloaded from: http:///
ds3150 10 of 28 1.2 transmitter transmit clock. the clock applied at the tclk input is us ed to clock in data on the tpos/tnrz and tneg pins. if the jitter attenuator is not enabled in the transmit path, the signal on tclk is the transmit line clock and must be transmission quality (i.e., 20ppm frequency accuracy and low jitter). if the jitter attenuator is enabled in the transmit path, the signal on tclk can be jittery and/or periodically gapped (not exceeding 8 ui) but must still have an average frequency within 20ppm of the nominal line rate. when enabled in the transmit path, the jitter attenuator generates the transmit line clock from the signal applied on the mclk pin. the signal on mclk mu st, therefore, be a transmission-quality clock ( 20ppm frequency accuracy and low jitter). the duty cycle of tclk is not restricted as long as the high and low times listed in section 3 are met. to support a glueless interface to a variety of neig hboring components, the polarity of tclk can be inverted using the ice input pin. see the ice pin description in table 2-a for details. framer interface format and the b3zs/hdb3 encoder. data to be transmitte d can be input in either nrz or bipolar format. to select the bipolar format, wire the zcse input pin high. in this format, the b3zs/hdb3 encoder is disabled, and the data to be transmitted is sampled on the tpos and tneg input pins. positive-polarity pulses are indicated by tpos = 1 while ne gative-polarity pulses are indicated by tneg = 1. tpos and tneg should not be active at the same time. to select the nrz format, wire zcse low. in this format, the b3zs/hdb3 encoder is enabled, and the data to be transmitted is sampled on the tnrz pin. the tneg pin is ignored in nrz mode and should be tied low. pattern generation. the transmitter can generate a number of different patterns internally, including unframed all ones (e3 ais), 1010?, and ds3 ais. see figure 1-5 for the structure of the ds3 ais signal. the tds0 and tds1 inputs are us ed to select these on-board patterns. table 2-b indicates the possible selections. waveshaping, line build-out, line driver. the waveshaping block converts the transmit clock, positive data, and negative data signals into a single ami signal that meets applicable telecommunications standards when transmitted on 75 coaxial cable. table 1-c through table 1-g and figure 1-4 show the waveform template specifications and test parameters from ansi t1.102, telcordia gr-253-core and gr-499- core, and itu-t g.703. because ds3 and sts-1 signals must meet the waveform templates at the cross-connect through any cable length from 0 to 450 feet, the waveshaping circuitry includes a selectable lbo feature. for cable lengths of 225 feet or greater, the lbo pin should be low. when lbo is low, output pulses are driven onto the coaxial cable without any preattenuation. fo r cable lengths less than 225 feet, lbo should be high. when lbo is high, pulses are preattenuated befo re being driven onto the coaxial cable. the lbo circuitry provides attenuation that mimics the attenuation of 225 feet of coaxial cable. to power down the transmitter and tri-state the tx+ and tx- output pins, pull the tts input pin low. interfacing to the line. the transmitter interfaces to the outgoing ds3/e3/sts-1 coaxial cable (75 ) through a 2:1 step-down transformer conn ected to the tx+ and tx- output pins. figure 1-2 shows the arrangement of the transformer and other recommended interface components. downloaded from: http:///
ds3150 11 of 28 transmit driver monitor. if the transmit driver monitor detects a faulty transmitter, it activates the dm output pin. when the transmitter is tri-stated ( tts = 0), the transmit driver monitor is also disabled. the transmitter is declared to be faulty when th e transmitter outputs see a load of less than about 25 . the dm pin is only available in the tqfp package. transmitter jitter generation (intrinsic). the transmitter meets the jitter generation requirements of all applicable standards, with or without the jitter attenuator enabled. transmitter jitter transfer. without the jitter attenuator enabled in the transmit side, the transmitter passes jitter through unchanged. with the jitter attenuator enabled in the transmit side, the transmitter meets the jitter transfer requirements of all applicable telecommunication standards in table 1-a . see figure 1-8 . table 1-c. ds3 waveform template time (in unit intervals) normalized amplitude equations upper curve -0.85 t -0.68 0.03 -0.68 t 0.36 0.5 {1 + sin[( /2)(1 + t/0.34)]} + 0.03 0.36 t 1.4 0.08 + 0.407e -1.84(t - 0.36) lower curve -0.85 t -0.36 -0.03 -0.36 t 0.36 0.5 {1 + sin[( /2)(1 + t/0.18)]} - 0.03 0.36 t 1.4 -0.03 table 1-d. ds3 waveform test parameters and limits parameter specification rate 44.736mbps ( 20ppm) line code b3zs transmission medium coaxial cable (at&t 734a or equivalent) test measurement point at the end of 0 to 450 feet of coaxial cable test termination 75 ( 1%) resistive pulse amplitude between 0.36v and 0.85v pulse shape an isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the curves listed in table 1-c . unframed all-ones power level at 22.368mhz between -1.8dbm and +5.7dbm unframed all-ones power level at 44.736mhz at least 20db less than the power measured at 22.368mhz pulse imbalance of isolated pulses ratio of positive and negative pulses must be between 0.90 and 1.10 downloaded from: http:///
ds3150 12 of 28 table 1-e. sts-1 waveform template time (unit intervals) normalized amplitude equations upper curve -0.85 t -0.68 0.03 -0.68 t 0.26 0.5 {1 + sin[( /2)(1 + t/0.34)]} + 0.03 0.26 t 1.4 0.1 + 0.61e -2.4(t - 0.26) lower curve -0.85 t -0.36 -0.03 -0.36 t 0.36 0.5 {1 + sin[( /2)(1 + t/0.18)]} - 0.03 0.36 t 1.4 -0.03 table 1-f. sts-1 waveform test parameters and limits parameter specification rate 51.840mbps ( 20ppm) line code b3zs transmission medium coaxial cable (at&t 734a or equivalent) test measurement point at the end of 0 to 450 feet of coaxial cable test termination 75 ( 1%) resistive pulse amplitude 0.800v nominal (not covered in specs) pulse shape an isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the curved listed in table 1-e . unframed all-ones power level at 25.92mhz between -1.8dbm and +5.7dbm unframed all-ones power level at 51.84mhz at least 20db less than the power measured at 25.92mhz downloaded from: http:///
ds3150 13 of 28 figure 1-4. e3 waveform template table 1-g. e3 waveform test parameters and limits parameter specification rate 34.368mbps ( 20ppm) line code hdb3 transmission medium coaxial cable (at&t 734a or equivalent) test measurement point at the transmitter test termination 75 ( 1%) resistive pulse amplitude 1.0v (nominal) pulse shape an isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the template shown in figure 1-4 . ratio of the amplitudes of positive and negative pulses at the center of the pulse interval 0.95 to 1.05 ratio of the widths of positive and negative pulses at the nominal half amplitude 0.95 to 1.05 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 time (ns) g.703 e3 template output level (v) 29.1ns 24.5ns 12.1ns 8.65ns 17ns downloaded from: http:///
ds3150 14 of 28 figure 1-5. ds3 ais structure m1 subframe x1 (1) 84 info bits f1 (1) 84 info bits c1 (0) 84 info bits f2 (0) 84 info bits c2 (0) 84 info bits f3 (0) 84 info bits c3 (0) 84 info bits f4 (1) 84 info bits m2 subframe x2 (1) 84 info bits f1 (1) 84 info bits c1 (0) 84 info bits f2 (0) 84 info bits c2 (0) 84 info bits f3 (0) 84 info bits c3 (0) 84 info bits f4 (1) 84 info bits m3 subframe p1 (0) 84 info bits f1 (1) 84 info bits c1 (0) 84 info bits f2 (0) 84 info bits c2 (0) 84 info bits f3 (0) 84 info bits c3 (0) 84 info bits f4 (1) 84 info bits m4 subframe p2 (0) 84 info bits f1 (1) 84 info bits c1 (0) 84 info bits f2 (0) 84 info bits c2 (0) 84 info bits f3 (0) 84 info bits c3 (0) 84 info bits f4 (1) 84 info bits m5 subframe m1 (0) 84 info bits f1 (1) 84 info bits c1 (0) 84 info bits f2 (0) 84 info bits c2 (0) 84 info bits f3 (0) 84 info bits c3 (0) 84 info bits f4 (1) 84 info bits m6 subframe m2 (1) 84 info bits f1 (1) 84 info bits c1 (0) 84 info bits f2 (0) 84 info bits c2 (0) 84 info bits f3 (0) 84 info bits c3 (0) 84 info bits f4 (1) 84 info bits m7 subframe m3 (0) 84 info bits f1 (1) 84 info bits c1 (0) 84 info bits f2 (0) 84 info bits c2 (0) 84 info bits f3 (0) 84 info bits c3 (0) 84 info bits f4 (1) 84 info bits note 1: x1 is transmitted first. note 2: the 84 info bits contain the sequence 101010?, where the first 1 immediately follows each x, p, f, c, or m bit . downloaded from: http:///
ds3150 15 of 28 1.3 diagnostics prbs generator and detector. the ds3150 contains on-board pseudorandom bit sequence (prbs) generator and detector circuitry for physical layer testing. the device genera tes and detects unframed 2 15 - 1 (ds3 or sts-1) or 2 23 - 1 prbs patterns compliant with the itu o.151 specification. the prbs generator is enabled through the tds0 and tds1 inputs ( table 2-a and table 2-b ). the prbs detector is always enabled and reports its status on the pr bs output pin. when the prbs detector is out of synchronization, the prbs pin is forced high. when the detector synchronizes to an incoming prbs pattern, the prbs pin is driven low and then puls es high, synchronous with rclk, for each bit error detected ( figure 1-6 and figure 1-7 ). the prbs detector and prbs pi n are only available in the tqfp package. figure 1-6. prbs output with normal rclk operation figure 1-7. prbs output with inverted rclk operation loopbacks. the ds3150 has two internal loopbacks ( figure 1-1 ). the analog loopback loops the outgoing transmit waveform back to the receiver inputs. this is a local or equipment loopback. during analog loopback data is transmitte d normally on tx+ and tx- but the incoming data on rx+ and rx- is ignored. the remote loopback loops recovered clock and data back through the liu transmitter. during remote loopback, recovered clock and data are output normally on rclk, rpos/rnrz and rneg/rlcv, but the tpos/tnrz and tneg pins are ignored. these two loopbacks are invoked using the lbks input pin ( table 2-a ). prbs detector is not in sync prbs detector is in sync; the prbs signal pulses high for each bit error detected rcl k prbs ice = 0 or 1 rcl k prbs prbs detector is not in sync prbs detector is in sync; the prbs signal pulses high for each bit error detected ice = float downloaded from: http:///
ds3150 16 of 28 1.4 jitter attenuator the ds3150 contains an on-board jitter a ttenuator (ja) that can be placed in the receive path or in the transmit path or disabled. this selection is made using the rmon and tts input pins. see table 2-c for selection details. figure 1-8 shows the minimum jitter attenuation for the device when the ja is enabled. figure 1-8 also shows the jitter transfer of the receiver when the ja is disabled. the jitter attenuator consists of a narrowband pll to retime the selected clock, a 16 x 2-bit fifo to buffer the associated data while the clock is bein g retimed, and logic to prevent over/underflow of the fifo in the presence of very large jitter amplitudes. the jitter attenuator requires a transmission-quality master clock (i.e., 20ppm frequency accuracy and low jitter). when enabled in the receive path, the ja can obtain its master clock from the mclk pin or the tclk pin. if the signal on the mclk pin is togglin g, the ja uses the signal on mclk as its master clock. if mclk is high or floating, the ja uses th e signal on the tclk pin as its master clock. when enabled in the transmit path, the ja must take its master clock from the mclk pin. the selected master clock is also used by the cl ock and data recovery block. the ja has a loop bandwidth of master_c lock / 2058874 (see corner frequencies in figure 1-8 ). the ja attenuates jitter at frequencies higher than the loop bandwidth while allowing jitter (and wander) at lower frequencies to pass throug h relatively unaffected. figure 1-8. jitter attenuation and jitter transfer 10 100 1k 10k 100k 1m 21.7hz (ds3) 16.7hz (e3) 25.2hz (sts-1) 1k -30 -20 -10 e3 [tbr24 (1997)] frequency (hz) jitter a ttenuation (db) 0 ds3 [gr-499 (1995)] category i ds3150 typical receiver jitter transfer with jitter attenuator disabled >1 50 k ds3150 ds3 / e3 / sts-1 minimum jitter attenuation with jitter attenuator enabled 40hz ds3 [gr-253 (1999)] category i 27hz sts-1 [gr-253 (1999)] category ii 40k 59.6k ds3 [gr-499 (1999)] category ii note: jitter attenuation and jitter transfer are not tested during production test. downloaded from: http:///
ds3150 17 of 28 2. pin descriptions pins are listed in alphabetical order. section 4 shows the pin configurations for both packages. table 2-a. pin descriptions name type function dm o active-low driver monitor (open drain). when the transmit driver monitor detects a faulty transmitter, dm is driven low. requires an external pullup to v dd . not bonded out in the plcc package. efe i3 (note 2) enhanced feature enable. efe enables the enhanced ds3150 features (prbs generation/detection and the transmission of patterns, including all ones, ds3 ais, and the 1010? pattern). 0 = enhanced features disabled: tds0 and tds1 ignored and prbs tri-stated 1 = enhanced features enabled: tds0, tds1, and prbs active loat = test mode enabled: tds0, tds1, lbo, los redefined as test pins ice i3 invert clock enable. ice determines on which rclk edge rpos/rnrz and rneg/rlcv are updated and on which tc lk edge tpos/tnrz and tneg are sampled. 0 = normal rclk/normal tclk: update rpos/rnrz and rneg/rlcv on falling edge of rclk; sample tpos/tnrz a nd tneg on rising edge of tclk 1 = normal rclk/inverted tclk: update rpos/rnrz and rneg/rlcv on falling edge of rclk; sample tpos/tnrz and tneg on falling edge of tclk float = inverted rclk/inverted tclk : update rpos/rnrz and rneg/rlcv on rising edge of rclk; sample tpos/tnrz and tneg on falling edge of tclk lbks i3 (note 2) active-low loopback select. lbks determines if either the analog loopback or the remote loopback is enabled. see the block diagram in figure 1-1 for details. 0 = analog loopback enabled 1 = no loopback enabled float = remote loopback enabled lbo i3 (note 2) line build-out. lbo indicates cable length for waveform shaping in ds3 and sts-1 modes. lbo is ignored for e3 mode and should be wired high or low. 0 = cable length 225ft 1 = cable length < 225ft los o active-low loss of signal. los is asserted upon detection of 175 75 consecutive zeros in the receive data stream. los is deasserted when there are no excessive zero occurrences over a span of 175 75 clock periods. an excessive zero occurrence is defined as three or more consecutive zeros in the ds3 and sts-1 modes or four or more zeros in the e3 mode. see section 1.2 for additional details. mclk i master clock. if the signal on mclk is toggling, the device assumes it is a transmission-quality clock (44.736mhz for ds3, 34.368mhz for e3, 51.840mhz for sts-1, 20ppm, low jitter) and uses it as its master clock. the duty cycle of the applied clock signal should be between 30% and 70%. if mclk is wired high or left floating, the device uses the signal on the tclk pin as the master clock. if mclk is wired low, the device takes its master clock from an internal oscillator. the frequency of this oscillator is determined by a resistor placed between the ofsel pin and v ss . mclk has an internal 15k pullup resistor to v dd . the selected master clock is used by the ja and cdr blocks. downloaded from: http:///
ds3150 18 of 28 name type function prbs o3 (note 3) prbs detector. the prbs pin reports the status of the prbs detector. the prbs detector constantly searches for either a 2 15 - 1 (ds3 or sts-1) or 2 23 - 1 (e3) pseudorandom bit sequence. when the prbs detector is out of synchronization, the prbs pin is driven high. when the detector synchronizes to an incoming prbs pattern, the prbs pin is driven low and then pulses high, synchronous with rclk, for each bit error detected. see figure 1-6 and figure 1-7 for more details. if efe = 0, the prbs pin is tri-stated. the prbs pin is only available in the tqfp package type. rclk o receive clock. the recovered clock is output on the rclk pin. the recovered data is updated at the rpos/rnrz and rneg/rlcv out puts on either the falling edge of rclk (ice = 0 or 1) or the rising edge of rclk (ice = float). during loss of signal ( los = 0), the rclk output signal is derived from the device?s master clock. rmon i3 (note 2) receive monitor mode. rmon determines whether or not the receiver?s preamp is enabled to provide flat to the incoming signal before it is processed by the equalizer. this feature should be enabled when the device is being used to monitor signals that have been resistively attenuated by a monitor jack. this input also controls the jitter attenuator ( table 2-c ). 0 = disable the monitor preamp, disable the jitter attenuator in the receive path 1 = enable the monitor preamp, disable th e jitter attenuator in the receive path float = disable the monitor preamp, enable the jitter attenuator in the receive path rneg/ rlcv o receive negative data or receive line code violation. when the b3zs/hdb3 decoder is disabled ( zcse = 1), rneg pulses high to indicate reception of a negative ami pulse. when the b3zs/hdb3 decoder is enabled ( zcse = 0), the nrz data stream is output on rnrz while rlcv is pulsed high for one rclk period whenever the decoder sees a line coding violation. rneg/rlcv is updated either on the rising edge of rclk (ice = float) or the falling edge of rclk (ice = 0 or 1). rpos/ rnrz o receive positive data or receive nrz data. when the b3zs/hdb3 decoder is disabled ( zcse = 1), rpos pulses high to indicate reception of a positive ami pulse. when the b3zs/hdb3 decoder is enabled ( zcse = 0), the nrz data stream is output on rnrz while rlcv is pulsed high whenever the decoder sees a line coding violation. rpos/rnrz is updated either on the rising edge of rclk (ice = float) or the falling edge of rclk (ice = 0 or 1). rx+, rx- i receive analog inputs. these differential ami inputs are coupled to the inbound 75 coaxial cable through a 1:2 step-up transformer ( figure 1-2 ). tclk i transmit clock. a ds3 (44.736mhz), e3 (34.368mhz), or sts-1 (51.840mhz) clock should be applied to the tclk pin. data to be transmitted is clocked into the device at tpos/tnrz and tneg either on the rising ed ge of tclk (ice = 0) or the falling edge of tclk (ice = 1 or float). the duty cycle on tclk is not restricted as long the high and low times listed in section 3 are met. see section 1.3 for additional details tds0 i3 (note 2) transmit data select bit 0. if efe = 1, tds0, tds1 and tess select the source of the transmit data ( table 2-b ). if efe = 0, tds0 is ignored. downloaded from: http:///
ds3150 19 of 28 name type function tds1/ ofsel i3 (note 2) transmit data select bit 1/oscillator frequency select. if efe = 1, tds1, tds0 and tess select the source of the transmit data ( table 2-b ). if efe = 0, tds1 is ignored. if mclk is wired low, tds1 is internally pulled low, and a resistor connected between this pin (ofsel) and ground determ ines the frequency of an internal oscillator. the following resistor values should be used for specific applications: e3: 6.81k , 2% ds3: 5.23k , 2% sts-1: 4.53k , 2% when switching among ds3, e3, and sts-1 modes, do not allow ofsel to float. instead, hardwire the highest resistor value and switch in series or parallel resistors as needed. example: for a ds3/e3 application, hardwire 5.23k ? for ds3 and switch in series 1.58k ? to get 6.81k ? for e3. tess i3 (note 2) t3/e3/sts-1 select. tess determines the mode of operation for the device. 0 = e3 1 = t3 (ds3) float = sts-1 tneg i3 (note 2) transmit negative data. when the b3zs/hdb3 encoder is disabled ( zcse = 1), tneg should be driven high to transmit a negative ami pulse. when the b3zs/hdb3 encoder is enabled ( zcse = 0), the nrz data stream should be applied to tnrz, while tneg is ignored and can be wired either high or low. tneg is sampled either on the falling edge of tclk (ice = 1 or float) or the rising edge of tclk (ice = 0). tpos/ tnrz i transmit positive data. when the b3zs/hdb3 encoder is disabled ( zcse = 1), tpos should be driven high to transmit a positive ami pulse. when the b3zs/hdb3 encoder is enabled ( zcse = 0), the nrz data stream should be applied to tnrz. tpos/tnrz is sampled either on the falling edge of tclk (ice = 1 or float) or the rising edge of tclk (ice = 0). tts i3 (note 2) transmit tri-state. tts determines whether the tx+ and tx- analog outputs are tri- stated or active. this input also controls the jitter attenuator ( table 2-c ). 0 = tri-state the transmit output driver, disable the jitter attenuator in the transmit path 1 = enable the transmit output driver, disabl e the jitter attenuator in the transmit path float = enable the transmit output driver, enable the jitter attenuator in the transmit path tx+, tx- o3 (note 3) transmit analog outputs. these differential ami outputs are coupled to the outbound 75 coaxial cable through a 2:1 step-down transformer ( figure 1-2 ). these outputs can be tri-stated using the tts input pin. v dd p positive supply. 3.3v 5%. all v dd pins should be wired together. v ss p ground reference. all v ss pins should be wired together. zcse i active-low zero code suppression enable. zcse has an internal 80k pullup to v dd . 0 = b3zs/hdb3 encoder/decoder enabled (nrz interface enabled) 1 = b3zs/hdb3 encoder/decoder disabled (bipolar interface enabled) note 1: pin type i = input pin. pin type o = output pin. pin type p = power-supply pin. note 2: pin type i3 is an input capable of detecting three states: high, low, and float. all i3 input s have an internal 13k pullup to approximately 1.5v. the voltage range of the float state is approximately 1.2v to 1.9v. if the functi on of the float state of a n i3 pin is not defined in table 2-a , then the float state is used for factory test only. note 3: pin type o3 is an output that is tri-state capable. downloaded from: http:///
ds3150 20 of 28 table 2-b. transmit data selection tds1 tds0 tess transmit mode selected 0 0 x transmit normal data clocked in on tpos/tnrz and tneg 0 1 x transmit unframed all ones 1 0 0 or float transmit unframed 101010? pattern 1 0 1 transmit ds3 ais ( figure 1-5 ) 1 1 0 transmit 2 23 - 1 prbs pattern (per itu o.151) 1 1 1 or float transmit 2 15 - 1 prbs pattern (per itu o.151) note: when efe is low, the device ignores tds0 and tds1 and always transmits normal data clocked in on tpos/t nrz and tneg. table 2-c. rmon and tts signal decode rmon tts receiver preamp transmit line driver jitter attenuator 0 0 disabled tri-stated disabled 0 1 disabled enabled disabled 0 float disabled enabled enabled in transmit path 1 0 enabled tri-stated disabled 1 1 enabled enabled disabled 1 float enabled enabled enabled in transmit path float 0 disabled tri-stated enabled in receive path float 1 disabled enabled enabled in receive path float float disabled enabled enabled in receive path downloaded from: http:///
ds3150 21 of 28 3. electrical characteristics absolute maximum ratings voltage range on any lead with respect to v ss (except v dd ) -0.3v to 5.5v supply voltage range (v dd ) with respect to v ss -0.3v to 3.63v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature range see ipc/jedec j-std-020 standard stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the devic e. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sect ions of t he specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect devic e reliability. note: the typical values listed below are not production tested. recommended dc operating conditions (t a = 0c to +70 c for ds3150q/t, t a = -40 c to +85 c for ds3150qn/tn.) parameter symbol min typ max units logic 1 v ih 2.4 5.5 v logic 0 v il -0.3 +0.8 v power supply v dd 3.135 3.465 v dc characteristics (v dd = 3.3v 5%, t a = 0c to +70 c for ds3150q/t, t a = -40 c to +85 c for ds3150qn/tn.) parameter symbol min typ max units e3 supply current (note 1) i dd 75 90 ma ds3 supply current (note 1) i dd 87 102 ma sts-1 supply current (note 1) i dd 95 110 ma power-down current (note 2) i pd 45 ma lead capacitance c io 7 pf input leakage (note 3) i il -10 +10 a input leakage (i3 pins or pins with internal pullup resistors) (note 3) i ilp -500 +500 a output leakage (prbs pin, when high-z) i lo -10 +10 a output current (v oh = 2.4v) i oh -4.0 ma output current (v ol = 0.4v) i ol +4.0 ma pullup resistor on i3 pins z i3 13 k note 1: tclk at 34.368mhz for e3, 44.736mhz for ds3, or 51.84mhz for sts-1; mclk floating; tx+/tx- driving all ones into 150 resistive load; all ones driven into rx+/rx- (1.0v square wave); all other inputs at v dd or grounded; all other outputs open. note 2: v dd = 3.465v; mclk = 44.736mhz and tts = 0; other inputs at v dd or grounded; other outputs left open-circuited. note 3: 0v < v in < v dd. downloaded from: http:///
ds3150 22 of 28 framer interface timing (v dd = 3.3v 5%, t a = 0c to +70c for ds3150q/t, t a = -40 c to +85 c for ds3150qn/tn.) ( figure 3-1 ) parameter symbol conditions min typ max units (note 4) 22.4 (note 5) 29.1 rclk/tclk clock period t1 (note 6) 19.3 ns (note 4) 9.0 11.2 13.4 (note 5) 11.6 14.5 17.4 rclk clock high/low time t2, t3 (note 6) 7.7 9.6 11.5 ns tclk clock high/low time t2, t3 7 ns tpos/tnrz, tneg to tclk setup time t4 2 ns tpos/tnrz, tneg hold time t5 2 ns rclk to rpos/rnrz valid, rneg/rlcv valid, state change on prbs t6 (notes 7, 8) 2 6 ns note 4: ds3 mode. note 5: e3 mode. note 6: sts-1 mode. note 7: in normal mode, tpos/tnrz and tneg are sampled on the rising edge of tclk and rpos/rnrz and rneg/rlcv are updated on the falling edge of rclk. note 8: in inverted mode, tpos/tnrz and tneg are sampled on the falling edge of tclk and rpos/rnrz and rneg/rlcv are updated on the rising edge of rclk. figure 3-1. framer interface timing diagram rclk (normal mode), tclk (inverted mode) tpos/tnrz, tneg rpos/rnrz, rneg/rlcv, prbs t4 t5 t6 t1 t2 t3 tclk (normal mode), rclk (inverted mode) downloaded from: http:///
ds3150 23 of 28 receiver input characteri stics?ds3 and sts-1 modes (v dd = 3.3v 5%, t a = 0c to +70 c for ds3150q/t, t a = -40 c to +85 c for ds3150qn/tn.) parameter min typ max units receive sensitivity (length of cable) 900 1200 feet signal-to-noise ratio, interfering si gnal test (notes 9, 10) 10 input pulse amplitude, rmon = 0 (notes 10, 11) 1300 mvpk input pulse amplitude, rmon = 1 (notes 10, 11) 260 mvpk analog los declare, rmon = 0 (note 12) -25 db analog los clear, rmon = 0 (note 12) -18 db analog los declare, rmon = 1 (note 12) -39 db analog los clear, rmon = 1 (note 12) -32 db intrinsic jitter generation (note 10) 0.03 ui p-p receiver input characteristics?e3 mode (v dd = 3.3v 5%, t a = 0c to +70 c for ds3150q/t, t a = -40 c to +85 c for ds3150qn/tn.) parameter min typ max units receive sensitivity (length of cable) 900 1200 feet signal-to-noise ratio, interfering si gnal test (notes 9, 10) 12 input pulse amplitude, rmon = 0 (notes 10, 11) 1300 mvpk input pulse amplitude, rmon = 1 (notes 10, 11) 260 mvpk analog los declare, rmon = 0 (note 12) -25 db analog los clear, rmon = 0 (note 12) -18 db analog los declare, rmon = 1 (note 12) -39 db analog los clear, rmon = 1 (note 12) -32 db intrinsic jitter generation (note 10) 0.03 ui p-p note 9: an interfering signal (2 15 - 1 prbs for ds3/sts-1, 2 23 - 1 prbs for e3, b3zs/hdb3 encoded, compliant waveshape, nominal bit rate) is added to the wanted signal. the combined signal is passed through 0 to 900 feet of coaxial cable and presented to the ds3150 receiver. this spec indicates the lowest signal-to-noise ratio that results in a bit error ratio < 10 -9 . note 10: not tested during production test. note 11: measured on the line side (the bnc connector side) of the 1:2 receive transformer ( figure 1-2 ). during measurement, incoming data traffic is unframed 2 15 - 1 prbs for ds3/sts-1 and unframed 2 23 - 1 prbs for e3. note 12: with respect to nominal 800mvpk signal for ds3/sts-1 and nominal 1000mvpk signal for e3. downloaded from: http:///
ds3150 24 of 28 transmitter output characteristics?ds3 and sts-1 modes (v dd = 3.3v 5%, t a = 0 to +70 c for ds3150q/t, t a = -40 c to +85 c for ds3150qn/tn.) parameter min typ max units ds3 output pulse amplitude, lbo = 0 (note 13) 700 800 900 mvpk ds3 output pulse amplitude, lbo = 1 (note 13) 580 700 800 mvpk sts-1 output pulse amplitude, lbo = 0 (note 13) 700 800 1100 mvpk sts-1 output pulse amplitude, lbo = 1 (note 13) 520 700 850 mvpk ratio of positive and negative pulse peak amplitudes 0.9 1.1 ds3 unframed all-ones power level at 22.368mhz, 3khz bandwidth -1.8 +5.7 dbm ds3 unframed all-ones power level at 44.736mhz, 3khz bandwidth -21.8 -14.3 dbm sts-1 power level, wideband (<200mhz) -2.7 +4.7 dbm intrinsic jitter generation (note 14) 0.02 0.05 ui p-p transmitter output characteristics?e3 mode (v dd = 3.3v 5%, t a = 0 to +70 c for ds3150q/t, t a = -40 c to +85 c for ds3150qn/tn.) parameter min typ max units output pulse amplitude (note 13) 900 1000 1100 mvpk pulse width 14.55 ns ratio of positive and negative pulse amplitudes (at centers of pulses) 0.95 1.05 ratio of positive and negative pulse widths (at nominal half amplitude) 0.95 1.05 intrinsic jitter generation (note 14) 0.02 0.05 ui p-p note 13: measured on the line side (the bnc connector side) of the 2:1 transmit transformer ( figure 1-2 ). note 14: output jitter generated by the transmitter with a jitter-free clock signal applied to the tclk pin. not tes ted during productio n test. downloaded from: http:///
ds3150 25 of 28 4. pin configurations lbo tds0 1 2 3 4 5 6 7 8 10 12 35 36 rx+ efe rx- v ss v dd l o s v ss tess tpos/tnrz tneg tt s rpos/rnrz rneg/rlcv rclk v ss rmon z cs e mclk tds1/ofsel v ss v dd v ss tx+ ice tx- v ss v ss l bk s v dd v ss v ss v ss v ss prbs 3433 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 11 9 4847 46 45 44 43 42 41 40 39 38 37 v ss v ss v dd v dd v ss tcl k v ss v ss d m v dd v ss v ss ds3150 tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 rx + efe rx- tds0 v dd l o s lbo tess tpos/tnrz tneg tcl k v dd tt s rpos/rnrz rneg/rlcv rclk v ss rmon z cs e mclk tds1/ofsel v ss v dd v ss tx+ ice tx- ds3150 plcc l bk s downloaded from: http:///
ds3150 26 of 28 5. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package out line info rmation, go to www.maxim-ic.com/dallaspackinfo .) 28-pin plcc dimensions: millimeters thermal information: ja = +68 c/w dim min max a 0.165 0.180 a1 0.090 0.120 a2 0.020 ? b 0.026 0.033 b1 0.013 0.021 c 0.009 0.012 d 0.485 0.495 d1 0.450 0.456 d2 0.390 0.430 e 0.485 0.495 e1 0.450 0.456 e2 0.390 0.430 l1 0.060 ? n 28 ? e1 0.050 bsc ch1 0.042 0.048 downloaded from: http:///
ds3150 27 of 28 48-pin tqfp dimensions: millimeters thermal information: ja = +46 c/w dim min max a ? 1.20 a1 0.05 0.15 a2 0.95 1.05 d 8.80 9.20 d1 7.00 bsc e 8.80 9.20 e1 7.00 bsc l 0.45 0.75 e 0.50 bsc b 0.17 0.27 c 0.09 0.20 downloaded from: http:///
ds3150 28 of 28 maxim/dallas semiconductor cannot assume responsibility for use of any circu itry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to chan ge the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa are registered trademarks of maxim integrated products, inc., and dallas semiconductor corporation. 6. revision history revision description 020602 official new product release. 062702 section 3: electrical characte ristics: dc characteristics tableadded i dd parameter for each device mode operation (e3, t3, sts-1 supply current over temperature). 072602 table 2-a. signal descriptions : < float = test mode (not recommended) was added to the lbo description for = 1. table 2-a. signal descriptions : note 1all i3 inputs have an internal 10k pullup to 1.5v. was changed to all i3 inputs have an internal 13k pullup to approximately 1.5v. the float state voltage range is approximately 1.2v to 1.9v. 010703 added g.824 and ets en 300 689 to table 1-a. extensive additional descrip tion was added to the receiver and transmitter sections, including an los discussion, jitter tole rance graphs, and rlcv discussion. added receiver input characteristics and transmitter output characteristics tables in section 3: electrical characteristics deleted section 6: applications 032904 section 3: electrical characteristics: transmitter output characteristicse3 mode . corrections were made to notes 13 a nd 14 (were originally transposed). references to hbd3 were changed to the correcthdb3. 082404 section 3: electrical characteristics: updated temperature ranges on the electrical tables to indicate the comm ercial temperature range (0 c to +70c) for ds3150q/t and industrial temperature range (-40c to +85c) for ds3150qn/tn. 012505 section 3: electrical characteristics: transmitter output c haracteristicsds3 and sts-1 modes table (page 24): the spec sts-1 output pulse amplitude, lbo = 0 changed the max limit from 900mvpk to 1100mvpk. for spec sts-1 output pulse amplitude, lbo = 1 changed the min limit from 580mvpk to 520mvpk and changed the max limit from 800mvpk to 850mvpk. 071305 added bullet to features list: automatic data squelching during los (page 1) section 1.1, loss-of-signal detector paragraph: changes mutes to squelches. downloaded from: http:///

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